The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a manufacturing method of a semiconductor device suitable for increasing the integration density of the electrode portions and miniaturizing device regions.
The rapidity at which the density device integration density progresses in recent years in the semiconductor IC devices is remarkable, and the pattern line width has been reduced to the order of sub-microns. Consequently, the required high accuracy of mask alignment in the photolithography for the manufacture of semiconductor devices is in the way of further miniaturization of semiconductor devices.
Above all else, since the source/drain regions of a MOS transistor have been difficult to miniaturize for the reason that the accuracy of mask alignment at the time of formation of electrodes of the source/drain regions which governs the occupation areas of the regions could not be attained to a required degree, it has heretofore been difficult to miniaturize the device occupation areas.
For this reason, there have been proposed methods for realizing a high integration density for the electrode portions by forming the electrode portions in a self-aligned fashion. To give an example, a method is disclosed in JP-B-5-81051 (published on Nov. 11, 1993) corresponding to JP-A-62-291176 (laid-open on Dec. 17, 1987).
The problem with the conventional manufacturing method is that it requires many manufacturing steps, to form electrodes of diffused layers (source/drain regions), including a step of depositing a molybdenum film on a poly-silicon film, a step of causing an impurity in a poly-silicon film to diffuse into the poly-silicon to form an impurity-doped poly-silicon film and a heat treatment step of making the molybdenum film react with the impurity-doped-poly-silicon film. This may decrease the throughput and production yield.